Increasing memory access speed is a key goal in the design of computer systems. Unfortunately, the switching speed and access speed of electronic memory devices have not kept pace with increases in the speed of central processing units (CPUs) that depend on such memory devices. When executing a program involving frequent memory transfers, a faster processor coupled to a slower memory inevitably must wait while the memory completes a read or write operation. As a result, memory cycle speed or frequency has become a serious bottleneck that is limiting the development of faster computer systems.
Within a memory device, certain components are principally responsible for limiting the switching time of the device. Both of the two major types of memory devices, DRAMs and static random access memory (SRAM) devices, have an array of memory cells and circuits for driving or writing the memory cells in a controlled way.
DRAM memory cells must be periodically refreshed to maintain the state recorded in the cells. A plurality of refresh circuits are provided, each of which is associated with a column and coupled to all the memory cells in that column. A refresh signal clocks the refresh circuits and triggers them to refresh the bitlines of the column associated with the refresh circuit.
FIG. 1A is a block diagram of a (n.times.n.times.1 bit) DRAM device 400. FIGS. 1B and 1C are block diagrams of portions of the device 400 of FIG. 1A. The DRAM device 400 comprises an array of memory cells 402a, 402b, 402c, 402d. Each memory cell 402a-402d consists of a memory pass transistor Q1 and a capacitor C1. One side of the capacitor C1 is connected to a cell plate voltage, denoted VCP. VCP has a constant value, and is typically generated on the DRAM device 400. The other side of the capacitor C1 is connected to the source terminal 404 of the memory pass transistor Q1. A wordline WL is coupled to the gate of the memory pass transistor Q1 and its drain 406 is coupled to one of two complementary bitlines BL, ZBL. Multiple memory pass transistors Q1 of different memory cells 402a-402d are connected to each bitline BL, ZBL, and each memory pass transistor Q1 is selected by a different wordline from among wordlines WL0 through WLn.
The memory cells 402a-402d are organized into a plurality of rows 414a through 414n. The memory cells 402a-402d also are organized into a plurality of columns 415a through 415n.
An external address 410 supplied on an address bus is coupled to a row address decoder/wordline generator 412, which is coupled to the wordlines WL0 through WLn. The external address 410 is also supplied over the address bus to a column address decoder 419.
Referring now to both FIG. 1A and FIG. 1B, column select lines 422 coupled the column address decoder 419 to column selection switches 426. A plurality of sense amplifiers 416a-416n, represented in FIG. 1A as a block of sense amplifiers 416, receive column select signals from the column selection switches 426. Each of the sense amplifiers 416 is coupled to bitlines BL0, ZBL0 of one of the columns 415a-415n. The sense amplifiers 416 are enabled and disabled using the ENABLE (logic high) and ZENABLE (logic low) signals shown in FIG. 1C.
External data 428 that is to be read from or written to the DRAM device 400 is supplied on a device data bus 429 to a plurality of read and write drivers 430. The read and write drivers 430 supply the data 428 to the column selection switches via a read/write data bus 424.
To read or write external data 428 to a memory cell 402a-402d located in one of the columns 415a-415n, a series of steps are carried out. First, the array of memory cells 402a-402d is "pre-charged." In the pre-charge state, each bitline BL, ZBL is driven to a potential of VBL through transistors T7 and T8 of the circuit shown in FIG. 1C. In other words, the potential of each pair of bitlines BL, ZBL is equalized.
The location of the memory cell 402a-402d that is to be written is identified by supplying an external address 410 to the DRAM device 400. The external address 410 is fed to a row address decoder/wordline generator 412, which decodes the external address into a row address. The row address decoder/wordline generator 412 also identifies and activates one of the wordlines 414a, 414n that corresponds to the row of the selected memory cell 402a-402d. Thus, applying an external address to the DRAM device 400 activates one of the wordlines.
When a wordline is asserted by the row address decoder/wordline generator 412, a small amount of charge is added to or removed from a bitline BL or ZBL, depending upon the connection of the selected memory pass gate Q1.
When one of the sense amplifiers 416 is enabled, by asserting the ENABLE line, equalization transistors T7 and T8 turn off, and a cross-coupled latch 418 consisting of T1 through T4 is enabled. Since a small amount of charge has been added/removed from one of the bitlines BL or ZBL, each of the bitlines BL and ZBL now have a slightly different potential. The cross-coupled latch 418 senses this small difference in potential. In response, the cross-coupled latch 418 drives one of the bitlines BL, ZBL to full V.sub.DD and the other bitline to ground (GND). Then data can be read from or written to one of the columns 415a, 415n. Such operations are collectively called "column operations".
As shown in FIG. 1B, when a column operation is initiated, a column address decoder 419 decodes the column address 420 into one of the column select lines (CSL) 422. The line selected from among the column select lines 422 connects one of the sense amplifiers 416a, 416b, 416c to a global bus 424 that comprises two lines designated Global Input/Output (GIO) and its complement ZGIO. For a read operation, data is read from the global bus 424 by a read amplifier.
In a write operation, complementary data is driven onto the lines GIO and ZGIO of the global bus 424 by a write driver, and the data in one of the sense amplifiers, such as sense amplifier 416a, is overwritten. That is, after the write operation the sense amplifier 416a and the memory cell 402a-402n connected to it by a memory pass transistor Q1 retains the data presented during the write operation.
The voltage differential between GIO and ZGIO is a prime factor in how fast the sense amplifier 416a can be overwritten by the data driven onto the global bus 424 by the write driver. Generally, the larger the differential, the faster the sense amplifier data will be overwritten.
Although FIG. 1A, FIG. 1B, and FIG. 1C show structure for a 1-bit architecture, the structure shown in the figures and the operational concepts described above may be used with an architecture having a width of any number of bits.
One prior memory circuit with a bitline driver circuit is shown in FIG. 1D. A data driver circuit 100 accepts a write enable (WE) signal 10 and a complement write data (ZWDD) signal 18 as inputs, and drives a bitline driver circuit 40. The bitline driver circuit 40 drives two complementary bitlines GIO and ZGIO that are connected to each cell in an array of memory cells. The designations GIO and ZGIO refer to the role of the bitlines as global input/output lines for the memory cells.
The WE signal 10 is fed to an inverter 12 that produces a complementary signal ZWE as its output and feeds a first input of a NOR gate 14 and a first input of a NOR gate 16. The ZWE signal also is fed to a delay circuit 30, comprising two series coupled inverters 32, 34. The delay circuit 30 is used to adjust signal timing so that the ZWE signal appears at a latch 25, described below, at the correct instant.
The ZWE signal is then inverted again through inverter 36 and provided as the enable signal to a bistable latch 25 formed by OR gate 20, NAND gate 22, OR gate 26, and NAND gate 28. The write data signal ZWDD 18 is coupled to the latch, in conventional fashion, directly to the OR gate 20 and through an inverter 24 to one input of the OR gate 26. As is conventional, when the WE signal is pulled high, the current ZWDD data is latched by latch 25 and the outputs 50, 52 will remain the same until WE is pulled low.
The output 50 of the latch 25 is coupled along with the ZWE signal at the inputs of a NOR gate 14. The complementary latch output 52 is similarly coupled along with ZWE at the inputs of a NOR gate 16. The output 42 of the NOR gate 14 and the output 44 of the NOR gate 16 are coupled to a bitline driver circuit 40. The bitline driver circuit 40 comprises a pair of low bit drive transistors 60, 62 each having its gate cross-coupled to a gate of a second pair of high bit drive transistors 64, 66. The source terminals of a first transistor in each pair, i.e., the transistors 60, 64, are coupled to the supply voltage V.sub.DD. The source terminals of the second transistor in each pair, i.e., the transistors 62, 66, are coupled to ground. The drain terminal of the first transistor in a pair is coupled to the drain terminal of the second transistor in each pair and to one of the bitlines 46, 48. As shown, the drain of transistor 60 is coupled to the drain of transistor 62 and to the GIO bitline 46. The drain of transistor 64 is coupled to the drain of transistor 66 and to the ZGIO bitline 48. In this configuration, the transistor pairs will conduct either V.sub.DD minus a transistor voltage drop, V.sub.T, or ground to the bitlines depending on the logic state of the outputs 42, 44. Thus, the outputs 42, 44 drive the complementary bitlines GIO 46 and ZGIO 48.
The circuit of FIG. 1D can be implemented in a metal oxide semiconductor (MOS) integrated circuit using known fabrication techniques.
In operation, to write data to the bitlines, a data bit is sent or fed to the write data line ZWDD and the WE line is pulled high. When WE is high, latch 25 latches the data at ZWDD. The NOR gate 14 and the NOR gate 16 then produce complementary outputs 42, 44. If ZWDD is has a value that is logic low, or zero, then a one is being written. In this case, low logic values are presented to both inputs of the NOR gate 16, yielding a high or one at its output 44. When the output 44 is high, cross-coupled transistors 60, 66 conduct, thereby conducting V.sub.DD -V.sub.T to the GIO line 46 and pulling the ZGIO line 48 to ground, which is consistent with writing a one to the GIO bitline 46. In contrast, if ZWDD is high, then the cross-coupled transistors will conduct in opposite states, so that a zero is written to the bitlines. Thus, when WE is pulled high, either a logic high level voltage of V.sub.DD -V.sub.T or ground will appear at each of ZGIO and GIO, depending on whether the value of ZWDD is high or low.
Although this approach produces complementary signals for driving a memory cell according to data that is to be written to the cell, this circuit has a significant disadvantage. The circuit in FIG. 1D can only supply a maximum voltage differential between GIO and ZGIO of V.sub.DD -V.sub.T. The differential voltage between GIO and ZGIO directly relates to how fast the memory device can be written. As a result, the circuit of FIG. 1D will limit the switching frequency of a memory device in which it is used, creating a bottleneck.